Oskar Mencer

Head of Computer Architecture Research Group (inactive)
Department of Computing, Imperial College London,
180 Queen's Gate, London SW7 2BZ, England.

Email: o.mencer _at_ imperial ac uk

recent article in Scientific Computing: HPC impact on Quality of Life and Prosperity

recent image, David Cameron and Angela Merkel with DFE, CeBIT 2014:

Open Spatial Programming at OpenSPL and The Movie

ball Recent Activities:

Publication: "Trading & Risk: What's Your Favorite Risk Flavor?", Wall Street and Technology, November 26, 2013.
Seminar: "Multiscale Dataflow Computing," MIT CRiBB Seminar, March 1, 2013.
Colloquium: "Multiscale Dataflow Computing: The Vertical Perspective," Stanford Computer Systems Colloquium, January 9, 2013.
Keynote: "Dataflow Supercomputing", ICFPT Conference, December 2012.
Lecture: "A Perspective on the Limits of Computation", The Royal Institution, May 2012.

ball Award Papers:

Haohuan Fu, Oskar Mencer, Wayne Luk, "Optimizing Residue Arithmetic on FPGAs"
Best Paper Award, International Conference on Field-Programmable Technology 2008 (ICFPT'08). December, 2008.

Kubilay Atasu, Oskar Mencer, Wayne Luk, Wayne Luk, Can Ozturan,"Fast Custom Instruction Identification by Convex Subgraph Enumeration",
Best Paper Award, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), Leuven, Belgium. July, 2008.

Recent Award: Special Golden Arrow. at Com.Sult 2012

ball Consulting Professor, Center for Computational Earth and Environmental Science, Stanford University, 2009/2010


Computer Architecture (I, II), Custom Computing, Hardware, Multimedia, Computer Graphics


Theory and practice, interaction of hardware and software systems. More specifically this includes domain specific representations of computation on the system level, the architecture level, and the bit-level, including programming methodologies that exploit spatial and temporal parallelism on all three levels with the objective of increasing computational speed while decreasing power consumption. My research interests include computer architecture from embedded processors to supercomputers, parallel programming and parallel architectures, computer arithmetic, custom computing, VLSI, CAD, compilers, dynamic optimization, algorithms and programming methodologies.

- Publications

- EPSRC Funded Projects

- PhD Thesis: "Rational Arithmetic Units in Computer Systems"

I am/have been serving on committees of the following international conferences: IEEE FCCM, IEEE COOL Chips, FPL, FPT, IEEE ASAP, ICS, ICCES, and DATE.

In the past I have also been employed at the Computer Architecture and Arithmetic Group at Stanford University, the Computing Sciences Center at Bell Labs, the Central Research Laboratory of Hitachi, Tokyo, and the DIGITAL Systems Research Center (->Compaq->HP) in Palo Alto.

ball Introduction to Custom Computing (slides)

ball Suggestions for writing technical papers