I am a final year PhD student interested in scalable verification techniques for data-parallel programs. My research interests are parallel programming, computer architecture and formal reasoning. Specifications and problems at the hardware/software boundary get me excited. My previous work in this area include proofs of correctness for cache-coherence protocols, memory models and the semantics of barriers. Currently, I am very interested in the formal semantics of GPU programs and automatically proving good properties about them. Accelerators are increasingly common and I don’t believe formal methods and verification techniques have caught up with programming them.
I have a background in industry as a research engineer at ARM where I worked on hardware and software at many levels of the system stack.
I am a key contributor to GPUVerify, a verification technique and tool for the automatic analysis of GPU kernels written in OpenCL and CUDA. At ARM I developed prototypes and tools for CPU virtualisation (now found in the ARMv7 architecture), cache coherence verification (now in AMBA4 ACE) and instruction set simulators (the Cortex-M1 simulator shipped in RVDS).
I am an advocate of reproducible and repeatable research that enables other researchers to build upon my work. The accompanying artifact to my OOPSLA'12 paper was approved by the OOPSLA evaluation committee and allows others to use GPUVerify and reproduce the experimental evaluation given in my paper.
A Sound and Complete Abstraction for Reasoning about Parallel Prefix Sums, ACM SIGPLAN Symposium on Principles of Programming Languages, 2014
Barrier Invariants: a Shared State Abstraction for the Analysis of Data-Dependent GPU Kernels, ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, 2013
GPUVerify: a Verifier for GPU Kernels, ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, 2012
IP Modeling and Verification, Book chapter in Processor and System-on-Chip Simulation (Springer), 2010
Stream Compilation for Real-Time Embedded Multicore Systems, IEEE/ACM International Symposium on Code Generation and Optimization, 2009
Reasoning about the ARM weakly consistent memory model, ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2008
The ARMv6M Architecture in Coq, Workshop on Hardware Design and Functional Languages, 2007