Hazard detection is the same as with forwarding : during ID we check whether the register being read is the same as one which will be written by some earlier instruction.
The instruction is delayed until the value it needs is generated :
A stall is therefore unavoidable. We need to implement a pipeline interlock mechanism:
Hazard detection is the same as with forwarding : during ID we check whether the register being read is the same as one which will be written by some earlier instruction.
The instruction is delayed until the value it needs is generated :