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IDEA: Allow instructions to issue out of order when dependencies
allow.
EXAMPLE:
DIVF R1, R2, R3
ADDF R4, R1, R5
SUBF R5, R5, R6
Here, ADDF is delayed waiting for result of DIVF.
Meanwhile SUBF can proceed. We must delay writing it's result, or
take some other action, or ADDF will get the wrong data.
- This is primarily of interest with long-running
operations such as FP arithmetic and memory accesses
- Low-latency operations (such as integer arithmetic)
are handled separately by a simple statically-scheduled
pipeline
(H&P pp.241)
Paul H J Kelly
Mon Dec 1 20:07:28 GMT 1997