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• CHAPTER 3
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• Control Hazards, Branch Prediction
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  • ``Cancelling'' branches
  • Branch delays in a deeper pipeline
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  • Run-time branch prediction
  • One-bit branch prediction
  • Performance of 1-bit prediction
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  • Two-bit branch prediction
  • Branch target prediction
  • The Branch Target Buffer
  • Implementation:
  • Branch folding
  • Control hazards: summary
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• Pipelining With Multicycle Operations
  • FP arithmetic components
  • Example: R4000 FPU
  • Supporting multiple outstanding FP operations
  • Structural hazards
  • Example:
  • OBSERVE
  • NEW DATA HAZARDS
  • WAR
  • WAW
  • Handling WAW hazards
  • PERFORMANCE
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• Dynamic Instruction Scheduling
  • Hazards
  • Instruction issue/overtaking
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  • In more detail...
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  • Scoreboard control
  • Costs of scoreboarding
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• Tomasulo's ``Register Renaming'' scheme
  • IDEA:
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  • How is this done?
  • THE SEQUENCE OF EVENTS
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  • STRUCTURAL HAZARDS
  • WAR HAZARDS
  • WAW HAZARDS
  • Register renaming
  • Memory accesses
  • Memory access disambiguation
  • TOMASULO : CONCLUSIONS
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• Multiple instructions/cycle
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  • Static 2 superscalar DLX
  • Increased effective delays
  • Static 2 superscalar - problems
  • Simplifying issue...
  • Static SS: Branch delays
  • IDEA: trace scheduling
  • Dynamic superscalar
  • Branches in a dynamic superscalar
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• Speculative Execution
  • Re-order buffer
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  • Tomasulo extended with ROB
  • Sequence of events
  • Re-order buffer: commit
  • Re-order buffer: branches
  • Re-order buffer: subtleties
  • Speculative execution: summary