Branch target prediction

Next: The Branch Target Buffer Up: Control Hazards, Branch Prediction Previous: Two-bit branch prediction

Branch target prediction

Predicting whether a branch is taken is not much use in DLX because we have already moved the test and target address calculation into ID
There is still a one-cycle branch delay
The nullifying delayed branch idea uses static prediction
How can we avoid the delay when dynamic prediction is correct?

Problem:

BEQZ R1,Label

IF

$\fbox{ID}$

EX

MEM

WB

successor 1

$\fbox{IF}$

ID

EX

MEM

WB

Need to know the address from which to load the next instruction
Before the branch has been decoded!

l|@ @*13p0.9em BEQZ R1,Label & IF & $\fbox{ID}$ & EX & MEM& WB
successor 1 & & $\fbox{IF}$ & ID & EX & MEM& WB

Need to know the address from which to load the next instruction
Before the branch has been decoded!

6in

BEQZ R1,Label

IF

$\fbox{ID}$

EX

MEM

WB

successor 1

$\fbox{IF}$

ID

EX

MEM

WB

Need to know the address from which to load the next instruction
Before the branch has been decoded!

l|@ @*13p0.9em BEQZ R1,Label & IF & $\fbox{ID}$ & EX & MEM& WB
successor 1 & & $\fbox{IF}$ & ID & EX & MEM& WB

Need to know the address from which to load the next instruction
Before the branch has been decoded!

Next: The Branch Target Buffer Up: Control Hazards, Branch Prediction Previous: Two-bit branch prediction