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Control Hazards, Branch Prediction


BEQZ R1,Label  IF ID EX MEM WB                
successor 1    IF stall stall IF ID EX MEM WB        
successor 2            IF ID EX MEM WB      
Cycle  1 2 3 4 5 6 7 8 9 A taken branch could cause a three-cycle delay in the DLX pipeline - two stalls and a repeated IF:
  • Condition is tested in EX
  • Branch target address is calculated during MEM stage (DLX branch is relative to PC) ((why??))
Even if the branch is not taken, we still suffer one stall.

Branches are common - 10% - 20%

(H&P pp.161)

       
l|@ @*13p0.9em BEQZ R1,Label & IF & ID & EX & MEM& WB
successor 1 & & IF & stall& stall& IF & ID & EX & MEM& WB
successor 2 & & & & & & IF & ID & EX & MEM& WB
Cycle & 1 & 2 & 3 & 4 & 5 & 6 & 7 & 8 & 9 A taken branch could cause a three-cycle delay in the DLX pipeline - two stalls and a repeated IF: Even if the branch is not taken, we still suffer one stall.

Branches are common - 10% - 20%

(H&P pp.161)



6in
BEQZ R1,Label  IF ID EX MEM WB                
successor 1    IF stall stall IF ID EX MEM WB        
successor 2            IF ID EX MEM WB      
Cycle  1 2 3 4 5 6 7 8 9 A taken branch could cause a three-cycle delay in the DLX pipeline - two stalls and a repeated IF:
  • Condition is tested in EX
  • Branch target address is calculated during MEM stage (DLX branch is relative to PC) ((why??))
Even if the branch is not taken, we still suffer one stall.

Branches are common - 10% - 20%

(H&P pp.161)

       
l|@ @*13p0.9em BEQZ R1,Label & IF & ID & EX & MEM& WB
successor 1 & & IF & stall& stall& IF & ID & EX & MEM& WB
successor 2 & & & & & & IF & ID & EX & MEM& WB
Cycle & 1 & 2 & 3 & 4 & 5 & 6 & 7 & 8 & 9 A taken branch could cause a three-cycle delay in the DLX pipeline - two stalls and a repeated IF: Even if the branch is not taken, we still suffer one stall.

Branches are common - 10% - 20%

(H&P pp.161)


 
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