Next: ...
Up: Control Hazards, Branch Prediction
Previous: Branch folding
- Branches are very common, often every 5 instructions or so
- Delayed branches rely on compile-time instruction
scheduling
- Cancelling delayed branches rely on static branch prediction
- 1-bit, 2-bit and cleverer dynamic prediction schemes
- 5% - 20% ``hard core'' of mispredicted branches
- Branch Target Buffer reduces delay for predicted branches to zero
- Misprediction delays must be minimised
- Large effective misprediction delay with multiple issue
and speculative execution