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FP arithmetic components
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Ch04-MoreSophisticatedCPUArchs
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Pipelining With Multicycle Operations
Up to now we have assumed that the EX and MEM stages can always be finished in one clock cycle.
This may be difficult or impossible to organise
Examples:
Integer multiply
Integer divide
Floating-point add, multiply
FP divide, square root etc
Cache misses
How does this complicate pipeline control?
(H&P pp.187,201)
FP arithmetic components
Example: R4000 FPU
Supporting multiple outstanding FP operations
Structural hazards
Example:
OBSERVE
NEW DATA HAZARDS
WAR
WAW
Handling WAW hazards
PERFORMANCE
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