Example: R4000 FPU

Add:

U

S+A

A+R

R+S

Mul:

U

E+M

M

M

M

M

N

N+A

R

Div:

U

A

R

D28

D+A

D+R

D+R

D+A

D+R

A

R

Cmp:

U

A

R

cycle

1

2

3

4

5

6

7

8

9

10

11

Table shows FP stages needed by each FP inst$^{\rm n}$ in each cycle:

U: Unpack FP numbers 
S: 		 Operand shift 
A: 		 Mantissa add 
R: 		 Rounding 
E: 		 Exception test 
M: 		 First stage of multiplier 
N: 		 Second stage of multiplier 
D: 		 Divide stage