Static 2superscalar DLX

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Static 2 $\times$ superscalar DLX

Inst $^{\rm n}$ packet: 1 FP & 1 anything else
Fetch 64-bits/cycle; Int on left, FP on right
Can only issue 2nd inst $^{\rm n}$ if 1st issues
Add ports for FP regs so FP load & FP op can issue together

Type Pipeline stages

Int. inst $^{\rm n}$ IF ID EX MEM WB

FP inst $^{\rm n}$ IF ID EX MEM WB

Int. inst $^{\rm n}$ IF ID EX MEM WB

FP inst $^{\rm n}$ IF ID EX MEM WB

Int. inst $^{\rm n}$ IF ID EX MEM WB

FP inst $^{\rm n}$ IF ID EX MEM WB

l|@ @*13p0.9em Type & Pipeline stages

6in

Type Pipeline stages

Int. inst $^{\rm n}$ IF ID EX MEM WB

FP inst $^{\rm n}$ IF ID EX MEM WB

Int. inst $^{\rm n}$ IF ID EX MEM WB

FP inst $^{\rm n}$ IF ID EX MEM WB

Int. inst $^{\rm n}$ IF ID EX MEM WB

FP inst $^{\rm n}$ IF ID EX MEM WB

l|@ @*13p0.9em Type & Pipeline stages

Next: Increased effective delays Up: Multiple instructions/cycle Previous: ...