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Increased effective delays


Int: LD \fbox{F0},100(R1)  IF ID EX \fbox{\sc mem}   WB                
FP: inst$^{\rm n}$  IF ID EX MEM WB                
Int: LD \fbox{R2},100(R1)    IF ID EX \fbox{\sc mem}   WB              
FP: inst$^{\rm n}$    IF ID EX MEM WB              
Int: inst$^{\rm n}$      IF ID EX MEM WB            
FP: ADDD F2,\fbox{F0},F1      IF ID \fbox{EX} MEM WB            
Int: ADD R4,\fbox{R2},R3        IF ID \fbox{EX} MEM WB          
FP: inst$^{\rm n}$        IF ID EX MEM WB          
  • Load delay is increased from 1 to at least 3, since inst$^{\rm n}$ in right half can't use it, nor inst$^{\rm n}$s in next slot
  • Needs more aggressive compiler inst$^{\rm n}$ scheduling

                          
l|@ @*13p0.9em Int: LD \fbox{F0},100(R1) & IF & ID & EX & \fbox{\sc mem}&  WB
FP: inst$^{\rm n}$ & IF & ID & EX & MEM& WB
Int: LD \fbox{R2},100(R1) & & IF & ID & EX & \fbox{\sc mem}&  WB
FP: inst$^{\rm n}$ & & IF & ID & EX & MEM& WB
Int: inst$^{\rm n}$ & & & IF & ID & EX & MEM& WB
FP: ADDD F2,\fbox{F0},F1 & & & IF & ID &\fbox{EX}& MEM& WB
Int: ADD R4,\fbox{R2},R3 & & & & IF & ID &\fbox{EX}& MEM& WB
FP: inst$^{\rm n}$ & & & & IF & ID & EX & MEM& WB
  • Load delay is increased from 1 to at least 3, since inst$^{\rm n}$ in right half can't use it, nor inst$^{\rm n}$s in next slot
  • Needs more aggressive compiler inst$^{\rm n}$ scheduling



6in
Int: LD \fbox{F0},100(R1)  IF ID EX \fbox{\sc mem}   WB                
FP: inst$^{\rm n}$  IF ID EX MEM WB                
Int: LD \fbox{R2},100(R1)    IF ID EX \fbox{\sc mem}   WB              
FP: inst$^{\rm n}$    IF ID EX MEM WB              
Int: inst$^{\rm n}$      IF ID EX MEM WB            
FP: ADDD F2,\fbox{F0},F1      IF ID \fbox{EX} MEM WB            
Int: ADD R4,\fbox{R2},R3        IF ID \fbox{EX} MEM WB          
FP: inst$^{\rm n}$        IF ID EX MEM WB          
  • Load delay is increased from 1 to at least 3, since inst$^{\rm n}$ in right half can't use it, nor inst$^{\rm n}$s in next slot
  • Needs more aggressive compiler inst$^{\rm n}$ scheduling

                          
l|@ @*13p0.9em Int: LD \fbox{F0},100(R1) & IF & ID & EX & \fbox{\sc mem}&  WB
FP: inst$^{\rm n}$ & IF & ID & EX & MEM& WB
Int: LD \fbox{R2},100(R1) & & IF & ID & EX & \fbox{\sc mem}&  WB
FP: inst$^{\rm n}$ & & IF & ID & EX & MEM& WB
Int: inst$^{\rm n}$ & & & IF & ID & EX & MEM& WB
FP: ADDD F2,\fbox{F0},F1 & & & IF & ID &\fbox{EX}& MEM& WB
Int: ADD R4,\fbox{R2},R3 & & & & IF & ID &\fbox{EX}& MEM& WB
FP: inst$^{\rm n}$ & & & & IF & ID & EX & MEM& WB

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Next: Static 2superscalar - problems Up: Multiple instructions/cycle Previous: Static 2superscalar DLX