Conclusion

The UltraSPARC-III processor is a high performance superscalar processor capable of issuing four instructions per cycle. It has a deep pipeline (14 stages), which helps in improving the performance, but can be very expensive during mispredictions. This is taken care of by having a miss queue which contains the sequential instructions, and these can be used for immediate processing. The performance is also improved by scaling both the instruction bandwidth and the latency. All these improvements, lead to a significant increase in the clock speed over the earlier generation of UltraSPARC processors, with UltraSPARC-III reaching a clock speed of 1Ghz. UltraSPARC-III also has enhanced test and debug capabilities, which proved to be very useful in keeping the costs down during the design and manufacturing phases of the processor.