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Ch02-PipelinedCPUArch
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Avoiding Stalls By Scheduling Instructions
Consider the common high-level language statement
a := b + c
We get
LW R1,B
IF
ID
EX
MEM
WB
LW R2,C
IF
ID
EX
MEM
WB
ADD R3,R1,R2
IF
ID
stall
EX
MEM
WB
SW, A,R3
IF
stall
ID
EX
MEM
WB
The stall seems inevitable. However, consider the sequence
a := b + c d := e - f
...
SUMMARY
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