Trying it yourself - simulation

2: Simulation, eg using Simplescalar (www.simplescalar.org)

Simplescalar is a parameterisable simulator with an instruction set based on MIPS. Compile your application using a special cross-compiler, then use one of the simulators:

 % ~phjk/simplescalar/bin/sslittle-na-sstrix-gcc -O3 MM.c
 % ~/simplescalar/simplesim-2.0/sim-cache ./a.out
...
ul2.miss_rate       0.4959 # miss rate (i.e., misses/ref)  
...

The default (unified) level-2 cache is 1024 sets $\times$ 64 bytes $\times$ 4-way set associative. You can select other configurations using a command-line parameter...

The SimpleScalar toolkit comes with other simulators which allow you to study other aspects of processor design.