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A taken branch could cause a three-cycle delay in the DLX pipeline - two
stalls and a repeated IF:
- Condition is tested in EX
- Branch target address is calculated during MEM stage
(DLX branch is relative to PC) ((why??))
Even if the branch is not taken, we still suffer one stall.
Branches are common - 10% - 20%
(H&P pp.161)
Paul H J Kelly
Mon Dec 1 20:07:28 GMT 1997