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Consider the MIPS R4000 pipeline structure:
- IF: first half of fetching of instrn; PC selection
happens here as well as initiation of I-cache access
- IS: second half of I-cache access
- RF: instruction decode and register fetch
- EX: ALU operation - arithmetic, effective address
calculation, branch target computation, condition evaluation
- DF: data fetch; first half of D-cache access
- DS: second half of D-cache access hit
- TC: tag check; determine whether the D-cache access was a hit
- WB: write back for loads and register-register
operations