External Memory Unit

This unit is responsible for the off-chip memory systems, like the level-two cache (L2) built with off-chip synchronous RAMs (SRAMs), and the main memory system built with off-chip synchronous DRAMs (SDRAMs). The L2 cache controller includes a 90-Kbyte on-chip tar RAM to support L2 cache sizes up to 8Mbytes. The main memory controller can support up to four banks of SDRAM memory totalling 4Gbytes of storage.

The L2 cache controller accesses off-chip L2 cache SRAMs with a 12-cycle latency to supply a 32-byte cache line to the L1-cache. A 256-bit wide data bus between the off-chip SRAMs and the microprocessor delivers the full 32 bytes of data needed for an L1 miss in a single SRAM cycle. The latency to main memory is further reduced by placing the tags for the L2 cache on-chip. This provides an additional advantage, as future designs can use these on-chip tag to build associative L2 caches without a latency penalty.