Visual Instruction Set

Graphics functionality is more and more in demand in today's workstations, with applications such as video conferencing, animation, live viewing of events etc. becoming part of everyday life. One of the ways to provide such high functionality was to add additional hardware to the existing hardware, like a graphics card. This can impact system performance, due to the addition of extra hardware, also the additional hardware has to be compatible with the existing hardware. Another solution is to add extra functionality to the existing instruction set architecture to take care of the additional requirements, this removes the need for extra hardware and also results in better overall system performance.

Visual Instruction Set (VIS) is a RISC-like extension to the SPARC V9 instruction set that provides instructions that enhance the graphic and image processing capabilities of the SPARC processors [4]. There is no need to perform memory mapped I/O or to access I/O devices in order to perform multimedia functions.

The implementation of VIS directly on UltraSPARC, coupled with the highly optimized memory system already developed for general purpose computing, allows UltraSPARC to support: Video conferencing, MPEG-2 decoding with full broadcast quality (720x480 pixels, 30 frames/sec), 3D visualization and stripped down systems where the CPU does all required graphics manipulation.

Most operations in VIS act on 4 pixel components in parallel. This coupled with UltraSPARC superscalar capabilities results in very high rates of parallel processing. [5] showed that using these features, MPEG decoding at 720x480x30 resolution could be done entirely in software, which was considered very difficult at that time due to unavailability of resources.