Main memory latency

For programs which are dominated by main memory latency, two techniques are used: a prefetch catch and an on-chip memory controller. The prefetch cache is a 2-Kbyte SRAM organized of 32 entries of 64 bytes and using four-way associativity with an LRU replacement policy. Data is prefetched into the prefetch cache utilizing 100% of the available main memory bandwidth. When a process needs data, it can just fetch it from the prefetch cache instead of going off-chip to main memory, which is expensive in terms of CPU cycles.