Data Cache Unit (on-chip memory system)

This unit comprises of the on-chip caches, namely the level-one (L1) cache. There are three first-level on-chip data caches: data - 64-Kbyte, four-way associative, 32-byte line; prefetch - 2-Kbyte, four-way associative, 64-byte line; and write - 2-Kbyte, four-way associative, 64-byte line.

The major philosophy in designing the on-chip memory system was: achieve uniform performance scaling by scaling both bandwidth and latency. The reason for scaling both bandwidth and latency was that some programs, due to inherent sequential dependence of data, do not have very good ILP and hence, just scaling bandwidth would not help.

Memory scaling issues are three prong: reducing average latency, reducing main memory latency, and scaling on-chip bandwidth.