Next: Main memory latency
Up: Data Cache Unit (on-chip
Previous: Data Cache Unit (on-chip
This is achieved by using a first-level sum-addressed memory
data cache [6]. Mixing the memory address adder with the word
line decoder for the data cache largely eliminates the address adder's
latency. This gives us a linear memory latency improvement.
Anandha Gopalan
2001-12-01