Multiple instructions/cycle

 

How can we reduce CPI to less than 1?

• ``Superpipelined'': Clock IS twice as fast as rest of CPU
• Very Long Instr Words (VLIW):
  • IF/ID/IS fetch & issue fixed no of inst s
  • Scheduled by the compiler
  • Unused issue slots are empty
  • As seen in Intel i860, Multiflow Trace, HP/Intel IA-64 (``Merced'') (?)
• Superscalar:
  • IF fetches large package of inst s then checks for hazards between them
  • Issues all inst s up to first hazard
  • Saves rest for next cycle
  • As seen in many modern CPUs

• ...
• Static 2 superscalar DLX
• Increased effective delays
• Static 2 superscalar - problems
• Simplifying issue...
• Static SS: Branch delays
• IDEA: trace scheduling
• Dynamic superscalar
• Branches in a dynamic superscalar
• ...