NANDA24: Novel Architecture and Novel Design Automation
The third 2-day workshop on Novel Architecture
and Novel Design Automation (NANDA) will take place at Imperial
College on 9-10 September 2024, hosted by Imperial’s Centre for High-performance
Embedded and Distributed Systems. The purpose of this workshop is to invite
renowned experts in the two areas of novel computer architecture and novel
design automation tools, to present their latest advances, and to provide a
forum to spark new ideas.
Our aim is to make this event a really
valuable landmark in the calendar for research in these areas, with a priority
on bringing interesting people together for interesting discussions!
Participation is open to all. Attending with a poster will make the experience
more valuable! You are also warmly encouraged to forward this invitation to
students, colleagues and collaborators, in academia and in industry.
We hope you'll be able to join us in September in London!
Registration
Please register to attend the
workshop here: https://estore.imperial.ac.uk/conferences-and-events/faculty-of-engineering/computing/nanda24
- Early Full
Registration (on or before 1st September): GBP 350
- Full Registration:
GBP 400
- Student
Registration: GBP 200
Programme
Monday 9 September 2024
0850 Welcome
0900 Saman Amarasinghe (MIT, USA): "Creating New Domain-Specific
Languages (DSLs) Made Easy"
0930 Maya Gokhale (LLNL, USA): “Purpose-built IP for High Performance Computing”
1000 Albert Cohen (Google Paris, France): “K-Pop Compilation: No Kernel Left Behind”
1030 break
1100 Gianfranco Bilardi (University of Padua, Italy): “Scalability of Architectures under Fundamental
Constraints”
1130 Nic Lane (University of Cambridge, UK): “Federated Learning is the Future of AI”
1200 Eiman Kanjo (Imperial and Nottingham Trent University, UK): “Tiny Models Deployment
on Modern MCUs”
1230 lunch and posters
1400 Christos Kozyrakis (Stanford University, USA): “AI Systems Architecture”
1430 John Wawrzynek (UC Berkeley, USA): "Hardware Design
for Machine Learning and Machine Learning for Hardware Design"
1500 Michaela Blott (AMD, Ireland): “Pervasive AI with Adaptive Computing”
1530 break and posters
1630 Andrew Putnam (Microsoft, USA): “Think Different: The Unique Role of FPGAs in a GPU-Dominated
World”
1700 Gustavo Alonso (ETHZ, Switzerland): “Data Processing in Energy Efficient Data Centers”
1800 dinner
Tuesday 10 September 2024
0900 Tulika Mitra (NUS, Singapore): “Spatial Accelerators at the Edge”
0930 Nabeel Shirazi (Intel, USA): "Grand Challenges for
FPGAs in the Next Decade"
1000 Jason Anderson (University of Toronto, Canada): “Coarse-Grained Reconfigurable Architectures
(CGRAs): Role as Accelerators and Architecture/CAD Challenges”
1030 break
1100 Christina Silvano (Poli di Milano)/Stefania Perri (U. Calabria), “Exploration of
Digital In-memory Computing to Accelerate Deep Learning on the Edge”
1130 Pedro Trancoso (Chalmers University, Sweden): “NextGen Accelerators: Flexible,
Scalable, Efficient – Together”
1200 Noa Zilberman (University of Oxford, UK): “In-Network ML: Inference at the Speed
of Data”
1230 lunch
1400 Jose Cano (University of Glasgow, UK): “Accelerating AI at the Edge: the Power of
Efficient Hardware-Software Co-Design”
1430 Stelios Venieris (Samsung, Cambridge, UK): “Beyond Status-Quo
NPUs: Hardware-Native Multi-Tenancy & Adaptive Inference”
1500 Suhaib Fahmy (KAUST, Saudi
Arabia): “It’s all about the primitives! Designing for high performance on
FPGAs”
1530 End
Call for Posters
We would like to invite you to submit a poster for
presentation at this workshop - simply to provide you with a concrete way
to initiate conversations about your interests. Posters will be reviewed
with a light-touch process, by a small committee of organisers and invited
speakers. Your poster can report on already-published work,
work-in-progress, and speculative research ideas - on topics including,
but not restricted to:
- Security, resilience and
power efficiency
- ASIC and FPGA design toolchain,
verification, test, synthesis
- Processor microarchitecture
- Instruction set design,
specification, verification, test
- Memory system architecture,
parallelism, coherency, disaggregation, PIM
- Datapath synthesis, approximate
computing, precision optimisation
- Accelerator synthesis, offload,
workload analysis and partitioning
- Performance instrumentation,
simulation methodology, design optimisation
- Hardware/software co-design,
static and dynamic analysis enabling architecture
- Domain-specific optimisation
For guidance on topics of interest, check out the talks
at NANDA’23 via Cassyni site, (and the NANDA’23
website) or email (p.kelly@imperial.ac.uk) and ask.
How
to submit your poster:
- Submissions may be made
at any time up to 30 August 2024.
- We aim to notify acceptance
of posters as quickly as possible, and early submissions are encouraged. If you submit your poster draft tomorrow
it could be accepted within a few days!
- Please submit pdf posters
for review via Easychair.
- If your poster submission
is accepted, please bring your paper poster with you to the event. You
may, of course, bring a revised and improved version!
Poster
design and formatting
- You will need to provide
a short abstract when submitting your poster, which we will use in the
online programme
- Posters should be no larger
than A0 size, landscape or portrait
- Make sure the title, authors
and affiliations are clearly shown at the top
- Text should be easily readable
from 2m (six feet) away
- Your objective is to get
the right people to engage with you in-person - you don’t have to tell the
whole story - but you do need to hook the viewer within 60 seconds. The
right image is probably the key!
There will be no formal proceedings, although we plan
a web-based record of the event, and posters can, optionally, be included there,
after the workshop.
NANDA’24 does not currently have
any industrial sponsors; if you would like to contribute, for example to enable
more PhD students to participate, please get in touch.