The following is a selected list of my publications, many of which are available on-line in pdf format. Your comments and suggestions will be very welcome - my homepage has the contact details.

• S. Liu, H. Fan, M. Ferianc, X. Niu, H. Shi and W. Luk, Toward full-stack acceleration of deep convolutional neural networks on FPGAs, Accepted for publication, IEEE Transactions on Neural Networks and Learning Systems, 2021.

• Z. Que, D.H. Noronha, R. Zhao, X. Niu, S.J.E. Wilton and W. Luk, In-circuit tuning of deep learning designs, Journal of Systems Architecture, Vol. 118, September 2021.

• K. Gao, W. Luk and S. Weston, High-frequency trading and financial time-series prediction with spiking neural networks, Wilmott, Vol. 2021, no. 113, pp. 18-23, May 2021.

• M. Ferianc, H. Fan, D. Manocha, H. Zhou, S. Liu, X. Niu and W. Luk, Improving performance estimation for design space exploration for convolutional neural network accelerators, Electronics, 10(4):520, February 2021.

• A. Gausen, W. Luk and C. Guo, Can we stop fake news? Using agent-based modelling to evaluate countermeasures for misinformation on social media, Workshop Proceedings of the 15th International AAAI Conference on Web and Social Media, 2021.

• N. Voss, B. Kwaadgras, O. Mencer, W. Luk and G. Gaydadjiev, On predictable reconfigurable system design, ACM Transactions on Architecture and Code Optimization, vol. 18, no. 2, Article 17, February 2021.

• M.C.W. Leong, K.H. Lee, B.P.Y. Kwan, Y.L. Ng, Z. Liu, N. Navab, W. Luk and K.W. Kwok, Performance-aware programming for intraoperative intensity-based image registration on graphics processing units, International Journal of Computer Assisted Radiology and Surgery, vol. 16, no. 3, pp. 375-386, 2021.

• I. Coleman, G. Corleone, J. Arram, H.C. Ng, L. Magnani and W. Luk, GeDi: applying suffix arrays to increase the repertoire of detectable SNVs in tumour genomes, BMC Bioinformatics, vol. 21, no. 1, Article 45, 2020.

• S. Cardamone, J.R.R. Kimmitt, H.G.A. Burton1, T.J. Todman, S. Li, W. Luk, and A.J.W. Thom, Field-programmable gate arrays and quantum Monte Carlo: Power efficient coprocessing for scalable high-performance computing, International Journal of Quantum Chemistry, vol. 119, no. 12, Article e25853, 2019.

• W. Li, C. He, H. Fu, J. Zheng, R. Dong, M. Xia, L. Yu and W. Luk, A Real-Time Tree Crown Detection Approach for Large-Scale Remote Sensing Images on FPGAs, Remote Sensing, vol. 11, no. 9, 1025, 2019.

• J. Xu, H. Fu, W. Shi, L. Gan, Y. Li, W. Luk and G. Yang, Performance tuning and analysis for stencil-based applications on POWER8 processor, ACM Transactions on Architecture and Code Optimization, vol. 15, no. 4, 41:1-41:25, 2019.

• J. Xu, G. Yang, H. Fu, W. Luk, L. Gan, W. Shi, W. Xue, C. Yang, Y. Jiang and C. He, Optimizing Finite Volume Method Solvers on Nvidia GPUs, IEEE Transactions on Parallel and Distributed Systems, vol. 30, no. 12, pp. 2790-2805, 2019.

• K.-H. Lee, K.C.D. Fu, Z. Guo, Z. Dong, M.C.W. Leong, C.-L. Cheung , A. P.-W. Lee, W. Luk and K.W. Kwok, MR Safe Robotic Manipulator for MRI-Guided Intracardiac Catheterization, IEEE/ASME Transactions on Mechatronics, vol. 23, no. 2, pp. 586-595, April 2018.

• X. Fan, D. Wu, W. Cao, W. Luk and L. Wang, Stream processing dual-track CGRA for object inference, IEEE Transactions on VLSI Systems, vol. 26, no. 6, pp. 1098-1111, 2018.

• S. Liang, S. Yin, L. Liu, W. Luk and S. Wei, FP-BNN: Binarized neural network on FPGA, Neurocomputing, vol. 275, pp. 1072-1086, January 2018.

• B. Cooper, S. Girdlestone, P. Burovskiy, G. Gaydadjiev, V. Averbukh, P.J. Knowles and W. Luk, Quantum chemistry in dataflow: density-fitting MP2, Journal of Chemical Theory and Computation, available online, October 2017.

• F.P. Russell, P.D. Duben, X. Liu, W. Luk and T.N. Palmer, Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures, Computer Physics Communications, available online, August 2017.

• A.-I. Funie, P. Grigoras, P. Burovskiy, W. Luk and M. Salmon, Run-time reconfigurable acceleration for genetic programming fitness evaluation in trading strategies, Journal of Signal Processing Systems, available online, May 2017.

• P. Burovskiy, P. Grigoras, S.J. Sherwin and W. Luk, Efficient assembly for high-order unstructured FEM meshes, ACM Transactions on Reconfigurable Technology and Systems, vol. 10, no. 2, Article 12, 2017.

• C. He, H. Fu, C. Guo, W. Luk and G. Yang, A fully-pipelined hardware design for Gaussian Mixture Models, IEEE Transactions on Computers, vol. 66, no. 11, pp. 1837-1850, November 2017.

• J. Yan, P.H.W. Leong, W. Luk and L. Wang, Lossless compression decoders for bitstreams and software binaries based on high-level synthesis, IEEE Transactions on VLSI Systems, vol. 65, no. 10, pp. 2842-2855, October 2017.

• L. Gan, H. Fu, W. Luk, C. Yang, W. Xue and G. Yang, Solving mesoscale atmospheric dynamics using a reconfigurable dataflow architecture, IEEE Micro, vol. 37, no. 4, pp. 40-50, August 2017.

• E. Hung, T. Todman and W. Luk, Transparent in-circuit assertions for FPGAs, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 7, 1193-1202, July 2017.

• J. Arram, T. Kaplan, W. Luk and P. Jiang, Leveraging FPGAs for accelerating short read alignment, IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol. 14, no. 3, May/June 2017.

• G. Inggs, D. Thomas and W. Luk, A domain specific approach to high performance heterogeneous computing, IEEE Transactions on Parallel and Distributed Systems, vol. 28, no. 1, pp. 2-15, 2017.

• T. Li, T. Heinis and W. Luk, ADvaNCE - efficient and scalable approximate density-based clustering based on hashing, Informatica, vol. 28, no. 1, pp. 105-130, 2017.

• K. Cheung, S.R. Schultz and W. Luk, NeuroFlow: A general purpose spiking neural network simulation platform using customizable processors, Frontiers in Neuroscience, 14 January 2016.

• J.M.P. Cardoso, J.G.F. Coutinho, T. Carvalho, P.C. Diniz, Z. Petrov, W. Luk and F. Goncalves, Performance driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach, Software: Practice and Experience, vol. 46, pp. 251-287, 2016.

• A.A.M. Bsoul, S.J.E. Wilton, K.H. Tsoi and W. Luk, An FPGA architecture and CAD flow supporting dynamically controlled power gating, IEEE Transactions on VLSI Systems, vol. 24, no. 1, pp. 178-191, January 2016.

• P.D. Duben, F.P. Russell, X. Niu, W. Luk and T.N. Palmer, On the use of programmable hardware and reduced numerical precision in earth-system modeling, Journal of Advances in Modeling Earth Systems, vol. 7, Issue 3, pp. 1393-1408, 2015.

• Q. Liu, T. Mak, T. Zhang, X. Niu, W. Luk and A. Yakovlev, Power-adaptive computing system design for solar-energy-powered embedded systems, IEEE Transactions on VLSI Systems, vol. 23, no. 8, pp. 1402-1414, August 2015.

• T. Todman, S. Stilkerich and W. Luk, In-circuit temporal monitors for runtime verification of reconfigurable designs, Design Automation Conference, 2015.

• X. Niu, W. Luk and Y. Wang, EURECA: On-chip configuration generation for effective dynamic data access, ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015.

• L. Gan, H. Fu, W. Luk, C. Yang, W. Xue, X. Huang, Y. Zhang and G. Yang, Solving the global atmospheric equations through heterogeneous reconfigurable platforms, ACM Transactions on Reconfigurable Technology and Systems, vol. 8, no. 2, Article 11, March 2015.

• S. Denholm, H. Inoue, T. Takenaka, T. Becker and W. Luk, Network-level FPGA acceleration of low latency market data feed arbitration, IEICE Transactions, 98-D(2), pp. 288-297, 2015.

• T.C.P. Chow, X. Niu, A. Eele, J. Maciejowski, P.Y.K. Cheung and W. Luk, Mapping adaptive particle filters to heterogeneous reconfigurable systems, ACM Transactions on Reconfigurable Technology and Systems, vol. 7, no. 4, Article 36, January 2015.

• X. Niu, Q. Jin, W. Luk and S. Weston, A Self-aware tuning and self-aware evaluation method for finite-difference applications in reconfigurable systems, ACM Transactions on Reconfigurable Technology and Systems, vol. 7, no. 2, Article 15, June 2014.

• C. Guo and W. Luk, Pipelined HAC estimation engines for multivariate time series, Journal of Signal Processing Systems, Volume 77, Issue 1-2, pp. 117-129, October 2014.

• T. Todman, S. Stilkerich and W. Luk, Using statistical assertions to guide self-adaptive systems, International Journal of Reconfigurable Computing, pp. 1-8, 2014.

• A. Le Masle and W. Luk, Mapping loop structures onto parametrized hardware pipelines, IEEE Transactions on VLSI Systems, vol. 22, no. 3, pp. 631-640, March 2014.

• E. Hung, T. Todman and W. Luk, Transparent insertion of latency-oblivious logic onto FPGAs, International Conference on Field Programmable Logic and Applications, 2014.

• C. Guo. W. Luk and S. Weston, Pipelined reconfigurable accelerator for ordinal pattern encoding, IEEE International Conference on Application-specific Systems, Architectures and Processors, 2014.

• Y. Wang, X. Zhou, L. Wang, J. Yan, W. Luk, C. Peng and J. Tong, SPREAD: A streaming-based partially reconfigurable architecture and programming model, IEEE Transactions on VLSI Systems, vol. 21, no. 12, pp. 2179-2192, December 2013.

• D.B. Thomas and W. Luk, Multiplierless algorithm for multivariate gaussian random number generation in FPGAs, IEEE Transactions on VLSI Systems, vol. 21, no. 12, pp. 2193-2205, December 2013.

• D.B. Thomas and W. Luk, The LUT-SR family of uniform random number generators for FPGA architectures, IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp. 761-770, April 2013.

• Y.M. Lam, K.H. Tsoi and W. Luk, Parallel neighbourhood search on many-core platforms, International Journal of Computational Science and Engineering, vol. 8, no. 3, pp. 281-293, 2013.

• S.A. Spacey, W. Luk, D. Kuhn and P.H.J. Kelly, Parallel partitioning for distributed systems using sequential assignment, Journal of Parallel and Distributed Computing, vol. 73, no. 2, pp. 207-219, February 2013.

• K.H. Tsoi, T. Becker and W. Luk, Modelling reconfigurable systems in event driven simulation, ACM SIGARCH Computer Architecture News, vol. 40, no.5, pp. 34-39, December 2012.

• T.C.P. Chau, W. Luk and P.Y.K. Cheung, Roberts: reconfigurable platform for benchmarking realtime systems, ACM SIGARCH Computer Architecture News, vol. 40, no.5, pp. 10-15, December 2012.

• N. Ng, N. Yoshida, X. Niu, K.H. Tsoi and W. Luk, Session types: towards safe and fast reconfigurable programming, ACM SIGARCH Computer Architecture News, vol. 40, no.5, pp. 22-27, December 2012.

• Q. Liu, T. Todman, W. Luk and G.A. Constantinides, Optimizing hardware design by composing utility-directed transformations, IEEE Transactions on Computers, vol. 61, no. 12, pp. 1800-1812, December 2012.

• M. Kurek and W. Luk, Parametric reconfigurable designs with Machine Learning Optimizer, Proc. International Conference on Field-Programmable Technology, 2012.

• S.A. Spacey, W. Luk, P. Kelly, and D. Kuhn, Improving communication latency with the write-only architecture, Journal of Parallel and Distributed Computing, vol. 72, no. 12, pp. 1617-1627, 2012.

• S.A. Spacey, W. Wiesemann, D. Kuhn and W. Luk, Robust software partitioning with multiple instantiation, INFORMS Journal on Computing, vol. 24, no. 3, pp. 500-515, 2012.

• C.Y. Yu, A.M. Smith, W. Luk, P.H.W. Leong and S.J.E. Wilton, Optimizing floating point units in hybrid FPGAs, IEEE Transactions on VLSI Systems, vol. 20, no. 7, pp. 1295-1303, July 2012.

• A.H.T. Tse, D. Thomas and W. Luk, Design exploration of quadrature methods in option pricing, IEEE Transactions on VLSI Systems, vol. 20, no. 5, pp. 818-826, May 2012.

• K. Atasu, W. Luk, O. Mencer, C. Ozturan, and G. Dundar, FISH: Fast Instruction SyntHesis for Custom Processors, IEEE Transactions on VLSI Systems, vol. 20, no. 1, pp. 52-65, January 2012.

• K.F.C. Yiu, Y. Lu, C.H. Ho, W. Luk, J. Hu and S. Nordholm, Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device, Digital Signal Processing, vol. 22, pp. 376-390, 2012.

• Q. Liu, T. Todman, W. Luk and G.A. Constantinides, Automated mapping of the MapReduce pattern onto parallel computing platforms, Journal of Signal Processing Systems, vol. 67, no. 1, pp. 65-78, 2012.

• J. Das, A. Lam, S.J.E. Wilton, P.H.W. Leong and W. Luk, An analytical model relating FPGA architecture to logic density and depth, IEEE Transactions on VLSI Systems, vol. 19, no. 12, pp. 2229-2242, December 2011.

• T. Mak, P.Y.K. Cheung, K.P. Lam and W. Luk, Adaptive routing in network-on-chips using a dynamic-programming network, IEEE Transactions on Industrial Electronics, vol. 58, no. 8, pp. 3701-3716, August 2011.

• M. Koester, W. Luk, J. Hagemeyer, M. Porrmann and U. Ruckert, Design optimizations for tiled partially reconfigurable systems, IEEE Transactions on VLSI Systems, vol. 19, no. 6, pp. 1048-1061, June 2011.

• K. Bertels, V.-M. Sima, Y. Yankova, G. Kuzmanov, W. Luk, G. Coutinho, F. Ferrandi, C. Pilato, M. Lattuada, D. Sciuto and A. Michelotti, HArtes: Hardware-software codesign for heterogeneous multicore platforms, IEEE Micro, vol. 30, no. 5, pp. 88-97, Sept.-Oct. 2010.

• H. Fu, O. Mencer and W. Luk, FPGA designs with optimized logarithmic arithmetic, IEEE Transactions on Computers, vol. 59, no. 7, pp. 1000-1006, July 2010.

• B. Cope, P.Y.K. Cheung, W. Luk and L. Howes, Performance comparison of graphics processors to reconfigurable logic: a case study, IEEE Transactions on Computers, vol. 54, no. 4, pp. 433-448, April 2010.

• P. Jamieson, T. Becker, P.Y.K. Cheung, W. Luk, T. Risa and T. Pitkanen, Benchmarking and evaluating reconfigurable architectures targeting the mobile domain, ACM Transactions on Design Automation of Electronic Systems (TODAES), Volume 15, Issue 2, Article 14, February 2010.

• T. Becker, P. Jamieson, Wayne Luk, P.Y.K. Cheung and T. Rissa, Power characterisation for fine-grain reconfigurable fabrics, International Journal of Reconfigurable Computing, vol. 2010, Article ID 787405, 2010.

• T.S.T. Mak, N.P. Sedcole, P.Y.K. Cheung and W. Luk, Wave-pipelined intra-chip signaling for on-FPGA communications, Integration, vol. 43, no. 2, pp. 188-201, 2010.

• Y.M. Lam, J.G.F. Coutinho, C.H. Ho, P.H.W. Leong and W. Luk, Multiloop parallelisation using unrolling and fission, International Journal of Reconfigurable Computing, vol. 2010, Article ID 475620, 2010.

• C.H. Ho, C.W. Yu, P.H.W. Leong, W. Luk and S.J.E. Wilton, Floating-point FPGA: architecture and modeling, IEEE Transactions on VLSI Systems, vol. 17, no. 12, pp. 1709-1718, December 2009.

• Q. Jin, D.B. Thomas, W. Luk and B. Cope, Exploring reconfigurable architectures for tree-based option pricing models, ACM Transactions on Reconfigurable Technology and Systems, Volume 2, Issue 4, Article 21, September 2009.

• H. Fu, W. Osborne, R.G. Clapp, O. Mencer and W. Luk, Accelerating seismic computations using customized number representations on FPGAs, EURASIP Journal on Embedded Systems, Article ID 382983, 2009.

• W.G. Osborne, W. Luk, J.G.F. Coutinho and O. Mencer, Energy reduction by systematic run-time reconfigurable hardware deactivation, Transactions on HiPEAC, 4(4), Issue 4 ,2009.

• S.A. Fahmy, P.Y.K. Cheung and W. Luk, High-throughput one-dimensional median and weighted median filters on FPGA, IET Proceedings - Computers and Digital Techniques, vol. 3, no. 4, pp. 384-394, July 2009.

• D. Lee, R. Cheung, W. Luk and J.D. Villasenor, Hierarchical segmentation for hardware function evaluation, IEEE Transactions on VLSI Systems, vol. 17, no. 1, pp. 103-116, January 2009.

• C.W. Yu, J. Lamoureux, S.J.E. Wilton, P.H.W. Leong and W. Luk, The coarse-grained/fine-grained logic interface in FPGAs with embedded floating-point arithmetic units, International Journal of Reconfigurable Computing, vol. 2008, Article ID 736203, 2008.

• S.S. Ang, G.A. Constantinides, W. Luk and P.Y.K. Cheung, Custom parallel caching schemes for hardware-accelerated image compression, Journal of Real-Time Image Processing, vol. 3, no. 4, pp. 289-302, December 2008.

• A. Fidjeland, W. Luk and S. Muggleton, A customisable multiprocessor for application-optimised inductive logic programming, Proc. Visions of Computer Science - BCS International Academic Conference, September 2008.

• J. Lamoureux and W. Luk, An overview of low-power techniques for field-programmable gate arrays, NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp. 338-345, 2008.

• D.B. Thomas and W. Luk, Multivariate Gaussian random number generation targeting reconfigurable hardware, ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 2, June 2008.

• D. Lee, R. Cheung, W. Luk and J.D. Villasenor, Hardware implementation trade-offs of polynomial approximations and interpolations, IEEE Transactions on Computers, vol. 57, no. 5, pp. 686-701, May 2008.

• S.J.E. Wilton, C.H. Ho, B. Quinton, P.H.W. Leong and W. Luk, A synthesizable datapath-oriented embedded FPGA fabric for silicon debug applications, ACM Transactions on Reconfigurable Technology and Systems, vol. 1, no. 1, March 2008.

• K. Atasu, C. Ozturan, G. Dundar, O. Mencer and W. Luk, CHIPS: Custom Hardware Instruction Processor Synthesis, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 3, pp. 528-541, March 2008.

• S. Yusuf, W. Luk, M. Sloman, N. Dulay, E.C. Lupu and G. Brown, Reconfigurable architecture for network flow analysis, IEEE Transactions on VLSI Systems, vol. 16, no. 1, pp. 57-65, January 2008.

• S.A. Fahmy, C.-S. Bouganis, P.Y.K. Cheung and Wayne Luk, Real-time hardware acceleration of the trace transform, Journal of Real-Time Image Processing, vol. 2, no. 4, pp. 235-248, December 2007.

• D.B. Thomas, W. Luk, P.H.W. Leong and J.D. Villasenor, Gaussian random number generators, ACM Computing Surveys, vol. 39, no. 4, pp. 11.1-11.38, October 2007.

• P. Sedcole, P.Y.K. Cheung, G.A. Constantinides and W. Luk, Run-time integration of reconfigurable video processing systems, IEEE Transactions on VLSI Systems, vol. 15, no. 9, pp. 1003-1016, September 2007.

• R.C.C. Cheung, D. Lee, W. Luk and J.D. Villasenor, Hardware generation of arbitrary random number distributions from uniform distributions via the inversion method, IEEE Transactions on VLSI Systems, vol. 15, no. 8, pp. 952-962, August 2007.

• D.B. Thomas and W. Luk, Non-uniform random number generation through piecewise linear approximations, IET Proceedings - Computers and Digital Techniques, vol. 1, no. 4, pp. 312-321, July 2007.

• K. De Bosschere, W. Luk, X. Martorell, N. Navarro, M. O'Boyle, D. Pnevmatikatos, A. Ramirez, P. Sainrat, A. Seznec, P. Stenstrm and O. Temam, High-Performance Embedded Architecture and Compilation Roadmap, Transactions on High-Performance Embedded Architectures and Compilers, vol. 1, no. 1, pp. 5-29, 2007.

• C.H. Ho, C.W. Yu, P.H.W. Leong, W. Luk and S.J.E. Wilton, Domain-specific hybrid FPGA: architecture and floating-point applications, Proc. International Conference on Field-Programmable Logic and Applications, pp. 196-201, August 2007.

• D.B. Thomas, J.A. Bower and W. Luk, Automatic generation and optimization of reconfigurable financial Monte-Carlo simulations, Proc. IEEE Int. conf. on Application-specific Systems, Architectures and Processors, 2007.

• J.G.F. Coutinho, M.P.T. Juvonen, J.L. Wang, B.L. Lo, W. Luk, O. Mencer and G.Z. Yang, Designing a posture analysis system with hardware implementation, Journal of VLSI Signal Processing, vol. 47, no. 1, pp. 33-45, April 2007.

• D.B. Thomas and W. Luk, High quality uniform random number generation using LUT optimised state-transition matrices, Journal of VLSI Signal Processing, vol. 47, no. 1, pp. 77-82, April 2007.

• D. Lee, A. Abdul Gaffar, R.C.C. Cheung, O. Mencer, W. Luk and G.A. Constantinides, Accuracy-guaranteed bit-width optimization, IEEE Transactions on Computer-Aided Design, vol. 25, no. 10, pp. 1990-2000, October 2006.

• J.A. Bower, W. Luk, O. Mencer, M.J. Flynn and M. Morf, Dynamic clock-frequencies for FPGAs, Microprocessors and Microsystems, vol. 30, no. 6, pp. 388-397, September 2006.

• D. Lee, J.D. Villasenor, W. Luk and P.H.W. Leong, A hardware Gaussian noise generator using the Box-Muller method and its error analysis, IEEE Transactions on Computers, vol. 55, no. 6, pp. 659-671, June 2006.

• S. McKeever and W. Luk, Provably-correct hardware compilation tools based on pass separation techniques, Formal Aspects of Computing, vol. 18, no. 2, pp. 120-142, June 2006.

• R. Dimond, O. Mencer and W. Luk, Application-specific customisation of multi-threaded soft processors, IEE Proceedings - Computers and Digital Techniques, vol. 153, no. 3, pp. 173-180, May 2006.

• D. Lee, A. Abdul Gaffar, O. Mencer and W. Luk, Optimizing hardware function evaluation, IEEE Transactions on Computers, vol. 54, no. 12, pp. 1520-1531, December 2005.

• C.T. Chow, L.S.M. Tsui, P.H.W. Leong, W. Luk and S.J.E. Wilton, Dynamic voltage scaling for commercial FPGAs, Proc. IEEE Int. Conf. on Field-Programmable Technology, 2005.

• R.C.C. Cheung, N. Telle, W. Luk, and P.Y.K. Cheung, Customisable Elliptic Curve Cryptosystems, IEEE Transactions on VLSI Systems, vol. 13, no. 9, pp. 1048-1059, September 2005.

• D. Lee, W. Luk, J.D. Villasenor, G. Zhang and P.H.W. Leong, A hardware Gaussian noise generator using the Wallace method, IEEE Transactions on VLSI Systems, vol. 13, no. 8, pp. 911-920, August 2005.

• T. Wiangtong, P.Y.K. Cheung and W. Luk, Hardware/software codesign: a systematic approach targeting data-intensive applications, IEEE Signal Processing, vol. 22, no. 3, pp. 14-22, May 2005.

• T. Todman, J.G. de F. Coutinho and W. Luk, Customisable hardware compilation, The Journal of Supercomputing, vol. 32, no. 2, pp. 119-137, May 2005.

• J.G. de F. Coutinho, J. Jiang and W. Luk, Interleaving behavioral and cycle-accurate descriptions for reconfigurable hardware compilation, Proc. IEEE Symposium on Field Programmable Custom Computing Machines, IEEE Computer Society Press, pp. 245-254, 2005.

• T.J. Todman, G.A. Constantinides, S.J.E. Wilton, O. Mencer, W. Luk and P.Y.K. Cheung, Reconfigurable computing: architectures and design methods, IEE Proceedings - Computers and Digital Techniques, vol. 152, no. 2, pp. 193-207, March 2005.

• G.A. Constantinides, P.Y.K. Cheung and W. Luk, Optimum and heuristic synthesis of multiple word-length architectures, IEEE Transactions on VLSI Systems, vol. 13, no. 1, pp. 39-57, January 2005.

• D. Lee, W. Luk, J.D. Villasenor and P.Y.K. Cheung, A Gaussian noise generator for hardware-based simulations, IEEE Transactions on Computers, vol. 53, no. 12, pp. 1523-1534, December 2004.

• H. Styles and W. Luk, Exploiting program branch probabilities in hardware compilation, IEEE Transactions on Computers, vol. 53, no. 11, pp. 1408-1419, November 2004.

• J. Gause, P.Y.K. Cheung and W. Luk, Reconfigurable computing for shape-adaptive video processing, IEE Proceedings - Computers and Digital Techniques, vol. 151, no. 5, pp. 313-320, September 2004.

• O. Mencer and W. Luk, Parameterized high throughput function evaluation for FPGAs, Journal of VLSI Signal Processing, vol. 36, no. 1, pp. 17-25, January 2004.

• G.A. Constantinides, P.Y.K. Cheung and W. Luk, Wordlength optimization for linear digital signal processing, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1432-1442, October 2003.

• G.A. Constantinides, P.Y.K. Cheung and W. Luk, Synthesis of saturation arithmetic architectures, ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 3, pp. 334-354, July 2003.

• T. Wiangtong, Peter Y.K. Cheung, W. Luk, Comparing three heuristic search methods for functional partitioning in hardware-software codesign, Journal on Design Automation for Embedded Systems, vol. 6, no. 4, pp. 425-449, July 2002.

• J. Gause, P.Y.K. Cheung and W. Luk, Reconfigurable shape-adaptive template matching architectures, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 2002.

• M. Weinhardt and W. Luk, Memory access optimisation for reconfigurable systems, Proc. IEE - Computers and Digital Techniques, vol. 148, no. 3, pp. 105-112, May 2001.

• N. Shirazi, D. Benyamin, W. Luk, P.Y.K. Cheung and S. Guo, Quantitative analysis of FPGA-based database searching, Journal of VLSI Signal Processing, vol 28, no. 1-2, May 2001.

• S.R. Guo and W. Luk, An integrated system for developing regular array designs, Journal of Systems Architecture, vol. 47, no. 3-4, pp. 315-337, April 2001.

• M. Weinhardt and W. Luk, Pipeline vectorization, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 2, pp. 234-248, February 2001.

• G.A. Constantinides, P.Y.K. Cheung and W. Luk, The multiple wordlength paradigm, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 2001.

• W. Luk, Synthesis route starts with instructions, EE Times, 16 February, 2001.

• N. Shirazi, W. Luk and P.Y.K. Cheung, Framework and tools for run-time reconfigurable designs, IEE Proceedings - Computers and Digital Techniques, vol. 147, no. 3, pp. 147-152, May 2000.

• S.D. Haynes, J. Stone, P.Y.K. Cheung and W. Luk, Video image processing with the Sonic architecture, IEEE Computer, vol. 33, no. 4, pp. 50-57, April 2000.

• H. Styles and W. Luk, Customising graphics applications: techniques and programming interface, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), IEEE Computer Society Press, 2000.

• S.D. Haynes, P.Y.K.Cheung, W.Luk and J. Stone, Sonic - a plug-in architecture for video processing, in Field-Programmable Logic and Applications, P. Lysaght, J. Irvine and R.W. Hartenstein (editors), LNCS 1673, pp. 21-30, Springer, 1999.

• W. Luk, T.K. Lee, J.R. Rice, P.Y.K. Cheung and N. Shirazi, Reconfigurable computing for augmented reality, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 136-145, IEEE Computer Society Press, 1999.

• M. Weinhardt and W. Luk, Pipeline vectorization for reconfigurable systems, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 52-62, IEEE Computer Society Press, 1999.

• W. Luk, P. Andreou, A. Derbyshire, F. Dupont-De-Dinechin, J. Rice, N. Shirazi and D. Siganos, A reconfigurable engine for real-time video processing, in Field-Programmable Logic and Applications, R.W. Hartenstein and A. Keevallik (editors), LNCS 1482, pp. 169-178, Springer, 1998.

• W. Luk and S. McKeever, Pebble: a language for parametrised and reconfigurable hardware design, in Field-Programmable Logic and Applications, R.W. Hartenstein and A. Keevallik (editors), LNCS 1482, pp. 9-18, Springer, 1998.

• N. Shirazi, W. Luk and P.Y.K. Cheung, Run-time management of dynamically reconfigurable designs, in Field-Programmable Logic and Applications, R.W. Hartenstein and A. Keevallik (editors), LNCS 1482, pp. 59-68, Springer, 1998.

• N. Shirazi, W. Luk and P.Y.K. Cheung, Automating production of run-time reconfigurable designs, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 147-156, IEEE Computer Society Press, 1998.

• W. Luk and S. Guo, Visualising reconfigurable libraries for FPGAs, in Proc. 31 Asilomar Conf. on Signals, Systems, and Computers, pp. 389-393, IEEE Computer Society Press, 1998.

• J.W. O'Leary, G.M. Brown and W. Luk, Verified compilation of communicating processes into clocked circuits, Formal Aspects of Computing, vol. 9, no. 5-6, pp. 537-559, 1998.

• P.I. Mackinlay, P.Y.K. Cheung, W. Luk and R.D. Sandiford, Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research, in Field-Programmable Logic and Applications, W. Luk, P.Y.K. Cheung and M. Glesner (editors), LNCS 1304, pp. 91-100, Springer 1997.

• W. Luk, N. Shirazi, S. Guo and P.Y.K. Cheung, Pipeline morphing and virtual pipelines, in Field-Programmable Logic and Applications, W. Luk, P.Y.K. Cheung and M. Glesner (editors), LNCS 1304, pp. 111-120, Springer 1997.

• W. Luk, N. Shirazi and P.Y.K. Cheung, Compilation tools for run-time reconfigurable designs, in Proc. IEEE Symposium on Field-Programmable Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 56-65, IEEE Computer Society Press, 1997.

• W. Luk, N. Shirazi and P.Y.K. Cheung, Modelling and optimising run-time reconfigurable systems, in Proc. IEEE Symposium on FPGAs for Custom Computing Machines, K.L. Pocek and J. Arnold (editors), pp. 167-176, IEEE Computer Society Press, 1996.

• W. Luk, S. Guo, N. Shirazi and N. Zhuang, A framework for developing parametrised FPGA libraries, in Field-Programmable Logic, Smart Applications, New Paradigms and Compilers, R.W. Hartenstein and M. Glesner (editors), LNCS 1142, pp. 24-33, Springer, 1996.

• G.M. Brown, W. Luk and J.W. O'Leary, Retargeting a hardware compiler using protocol converters, Formal Aspects of Computing, vol. 8, no. 2, pp. 209-237, 1996.

• M. Aubury and W. Luk, Binomial filters, Journal of VLSI Signal Processing, vol. 12, no. 1, pp. 35-50, January 1996.

• J. He, G. Brown, W. Luk and J. O'Leary, Deriving two-phase modules for a multi-target hardware compiler, in Designing Correct Circuits, Springer Electronic Workshop in Computing series, 1996.

• G. Brown, W. Luk and J.W. O'Leary, Retargeting a hardware compiler using protocol converters, Formal Aspects of Computing, vol. 8, no. 2, pp. 209-237, 1996.

• S. Guo and W. Luk, Compiling Ruby into FPGAs, in Field Programmable Logic and Applications, W. Moore and W. Luk (editors), LNCS 975, pp. 188-197, Springer, 1995.

• S. Guo and W. Luk, Producing design diagrams from declarative descriptions, in Proceedings of the Fourth International Conference on CAD/CG, S. Yand, J. Zhou and C. Li (editors), pp. 1084-1093, SPIE, 1995.

• A. Lawrence, A. Kay, W. Luk, T. Nomura and I. Page, Using reconfigurable hardware to speed up product development and performance, in Field Programmable Logic and Applications, W. Moore and W. Luk (editors), LNCS 975, Springer, pp. 111-118, 1995.

• G. Brown, W. Luk and J.W. O'Leary, Retargeting a hardware compiler proof using protocol converters, in Proc. International Symposium on Advanced Research in Asynchronous Circuits and Systems, IEEE Computer Society Press, 1994.

• W. Luk, D. Ferguson and I. Page, Structured hardware compilation of parallel programs, in More FPGAs, W. Moore and W. Luk (editors), Abingdon EE&CS Books, 1994.

• S. Guo, W. Luk and P. Probert, Developing parallel architectures for ranging and image sensors, in Proc. IEEE International Conference on Robotics and Automation, pp. 2205-2210, 1994.

• W. Luk and T. Wu, Towards a declarative framework for hardware-software codesign, in Proc. Third International Workshop on Hardware/Software Codesign, pp. 181-188, IEEE Computer Society Press, 1994.

• W. Luk, T. Wu and I. Page, Hardware-software codesign of multidimensional algorithms, in Proc. IEEE Workshop on FPGAs for Custom Computing Machines, D.A. Buell and K.L. Pocek (editors), pp. 82-90, IEEE Computer Society Press, 1994.

• W. Luk, Systematic serialisation of array-based architectures, Integration, the VLSI Journal, vol. 14, no. 3, pp. 333-360, February 1993.

• W. Luk, Pipelining and transposing heterogeneous array designs, Journal of VLSI Signal Processing, vol. 5, no. 1, pp. 7-20, January 1993.

• W. Luk, V. Lok and I. Page, Hardware acceleration of divide-and-conquer paradigms: a case study, in Proc. IEEE Workshop on FPGAs for Custom Computing Machines, D.A. Buell and K.L. Pocek (editors), pp. 192-201, IEEE Computer Society Press, 1993.

• I. Page and W. Luk, Compiling occam into FPGAs, in FPGAs, W. Moore and W. Luk (editors), pp. 271-283, Abingdon EE&CS Books, 1991.

• W. Luk, Optimising designs by transposition, in Designing Correct Circuits, G. Jones and M. Sheeran (editors), pp. 332-354, Springer-Verlag, 1991.

• W. Luk and G. Brown, A systolic LRU processor and its top-down development, Science of Computer Programming, vol. 15, no. 23, pp. 217-233, December 1990.

• W. Luk, Analysing parametrised designs by non-standard interpretation, in Proc. International Conference on Application-Specific Array Processors, S.Y. Kung, E. Swartzlander, J.A.B. Fortes and K.W. Przytula (editors), pp. 133-144, IEEE Computer Society Press, 1990.

• W. Luk, G. Jones and M. Sheeran, Computer-based tools for regular array design, in Systolic Array Processors, J. McCanny, J. McWhirter and E. Swartzlander (editors), pp. 589-598, Prentice-Hall International, 1989.

• W. Luk and G. Jones, Systolic recursive filters, IEEE Transactions on Circuits and Systems, vol. 35, no. 8, pp. 1067-1068, August 1988.